Mostek MK 36000 and MK 38000 chips are prior art with regard to this invention. These chips are n-channel silicon gate metal oxide silicon (MOS) 64K-bit read only memories (ROMs) organized respectively in 8192 words by eight bits and 32,768 words by eight bits.
In the MK36000 device, static storage cells with clocked control permit the circuit to be put into an automatic low power standby mode, reducing power dissipation to typically 35 mW. Chip operation is edge activated which permits greater system flexibility and an increase in system speed. The MK38000 device provides maximum circuit density while maintaining low power dissipation.
These memories both are arranged as an array of cells, which may be configured in an "x-cell" format. This array comprises a plurality of row leads each connected at a plurality of points to the gates of a corpesponding plurality of MOS transistors. Orthogonal to these rowlines are a plurality of connecting said plurality of transistors at their respective source and drains.
To determine the state of a given transistor in the array--that is to read or access the transistor its row is first taken high, its column line is pulled low while all other column lines are maintained high, the bit lines adjacent the low column line are inspected for current passage. If no current flow is detected, the transistor is deemed to have been in high state.
This sensing scheme of course views conditions at two adjacent transistors. In prior art n-channel ROMs, each bit and column line is attached to V.sub.cc through an n-channel transistor having its gate also attached to V.sub.cc. Column select is accomplished by turning on associated n-channel transistors.
By setting column select high, the selected column goes low and the pass transistors are enabled to pass data from the bit lines to the output lines. Accordingly, the selected transistor in the memory array must slew both the bit line, the pass transistor and the particular output line.